Conductive metal interconnect structures are formed to electrically connect source/drain regions and conductive features of an integrated circuit. The interconnect structures are conventionally formed by patterning and etching a dielectric material layer to form a trench therein, depositing a liner/barrier layer, typically a combination of layers, such as of titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and/or cobalt (Co), to line the side surfaces and bottom of the trench, and depositing a conductive material, such as tungsten (W) or copper (Cu), to fill the trench. The liner/barrier layers are provided to prevent diffusion of conductive material into the dielectric material layer and to enhance adhesion of the conductive material to the walls of the trench.
However, the use of ruthenium liners with copper can lead to formation of a galvanic cell, leading to copper corrosion and active copper ions. The copper ions may migrate over the upper surfaces of the liners to the dielectric material, leading to time dependent dielectric breakdown (TDDB). Therefore, improved methods for fabricating integrated circuits with ruthenium-lined copper interconnect structures are desired. Specifically, such methods are desired to prevent formation of galvanic cells, copper corrosion, and copper ion migration into dielectric material.
Accordingly, it is desirable to provide methods for fabricating integrated circuits with ruthenium-lined copper interconnect structures. In addition, it is desirable to provide methods for fabricating integrated circuits which avoid copper corrosion and contamination of dielectric material with copper. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.